1. Field of the Invention
The present invention relates generally to integrated circuit clocking and, more specifically, the present invention relates to optical clocking distribution networks in integrated circuits.
2. Description of Related Art
Microelectronic devices that use an integrated circuit (IC) chip rely upon a clocking signal that is relayed throughout the chip. To make a microelectronic device more reliable, the clocking signal needs to arrive simultaneously at several sites on the device. Clock skew is the difference in arrival times of clocking signals to different parts of the chip. Synchronous digital logic requires precise clocking signal arrival for the latching data. One present standard in the industry is that clock skew budget is approximately 10% of the cycle time. Hence for a 1 GHz clock frequency, which corresponds to a 1 ns cycle time, the tolerable clock skew is less than or equal to 100 ps. As VLSI clock frequencies increase beyond 1 GHz, the necessity to reduce clock skew becomes more challenging.
Global clock distribution network clock skew is typically controlled by the use of hierarchical H-trees as are well known in the art. As integrated circuits continue to become larger, more complex, and run at higher frequencies, previous clock skew standards become unacceptable. Even with a hierarchical H-tree network, the hierarchical H-tree network clock lines do not always have uniform characteristic impedance. As a result, there may be a non-uniform propagation delay of a clocking signal traveling through the paths of the hierarchical H-tree network even though nodes may be equal distances from the clock driver.
Prior art global clocking signal distribution networks that used electrical wiring consumed a significant amount of IC chip area as well as power. For instance, the global clocking signal distribution on today""s high speed IC chips typically accounts for approximately 10% of the chip power.
Some recent techniques include an optical clocking signal distribution network. In an optical clocking signal distribution network, an off chip optical source generates an optical clocking signal which is split with an optical splitter and a direct line of sight is provided to detectors through multiple openings in the back or inactive surface of the chip.
A major difficulty with the prior art optical clocking signal distribution is the difficulty in implementing it for advanced packaging technologies such as Control Collapse Chip Connection (C4) packaged chips, also referred to as flip chips. For C4 packaging, the front or active surface of the chip is hindered in its availability for optical signal access because the front surface of the chip is inverted and hidden from access. Consequently, C4 technology has lead to the development of an optical clocking signal distribution that enters the chip through the back surface.
Another important problem with an optical clocking signal distribution network is locating detectors in the direct line of sight of split optical clocking signals through the back surface of the chip. The requirement of several direct lines of sight through the back surface of the chip causes several problems. One problem is that several optical clocking signal landing zones on the back surface of the chip restricts the amount of available heat sink contact area on the back surface of the chip. With limited heat sink contact area, heat management becomes more difficult.
Another problem is that an optical clocking signal that enters the chip in the semiconductor substrate such as monocrystalline or polycrystalline silicon, must have a working wavelength that is long enough to pass through the semiconductor substrate. Relatively long wavelength optical clocking signals cause the responsivity of the signal receivers to decrease. This decrease in responsivity is due to the fact that the optical receivers are not as sensitive to the relatively long wavelength optical clocking signals as they are to relatively shorter wavelength optical clocking signals. Another problem is that optical signal receivers that obtain a signal from the back surface of the chip are more inefficient in operation than receivers that obtain a signal from the front of the chip because the optical signals must physically penetrate the substrate. Consequently, an optical clocking signal that impinges upon a receiver from the back side thereof results in a lower responsivity for reasons set forth above.
Yet another problem with back surface optical clocking signal distribution arises where many optical access recesses, and the necessary thinning, in the semiconductor substrate may weaken the chip and package as well as reduce thermal management abilities. Additionally, added profile height is necessary for the entire package because of the presence of an optical splitter.
What is needed is an optical clocking signal distribution system that overcomes the problems in the prior art.
Disclosed is an optical clocking signal distribution article that comprises a substrate that has a front surface and a back surface that are parallel planar. A dielectric layer is disposed upon the front surface, and a recess in the substrate exposes a portion of the dielectric layer when viewed through the back surface. A first light reflecting structure is disposed in the dielectric layer. The first light reflecting structure is disposed within the exposed portion of the dielectric layer. At least one light receiver is disposed upon the front surface.
Also disclosed is a method of forming an optical distribution structure. The method comprises forming a recess through a substrate to expose a dielectric layer. The method further comprises forming a waveguide in the dielectric layer, wherein the waveguide has a length, a width, a first end, and a second end, and wherein the recess is disposed over the first end of the waveguide. The method also comprises forming a first light reflecting structure at the first end of the waveguide.